Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

Details Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture Fast and Accurate Transaction Level Modeling of an Extended AMBA2.0 Bus Architecture

2007-10-25

arxiv.org/abs/0710.4808v1

Dans Design, Automation and Test in Europe | Designers'Forum - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

Transaction Level Modeling (TLM) approach is used to meet the simulation speed as well as cycle accuracy for large scale SoC performance analysis. We implemented a transaction-level model of a proprietary bus called AHB+ which supports an extended AMBA2.0 protocol. The AHB+ transaction-level model shows 353 times faster than pin-accurate RTL model while maintaining 97% of accuracy on average. We also present the development procedure of TLM of a bus architecture.

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