Simulations of gated Si nanowires and 3-nm junctionless transistors

Details Simulations of gated Si nanowires and 3-nm junctionless transistors Simulations of gated Si nanowires and 3-nm junctionless transistors

2010-03-24

arxiv.org/abs/1003.4631v1

Appl. Phys. Lett. 97, 062105 (2010)

Physics

Condensed Matter

Mesoscale and Nanoscale Physics

Scientific paper

10.1063/1.3478012

Inspired by recent experimental realizations and theoretical simulations of thin silicon nanowire-based devices, we perform predictive first-principles simulations of junctionless gated Si nanowire transistors. Our primary predictions are that Si-based transistors are physically possible without major changes in design philosophy at scales of ~1 nm wire diameter and ~3 nm gate length, and that the junctionless transistor may be the only physically sensible design at these length scales. We also present investigations into atomic-level design factors such as dopant positioning and concentration.

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