Underlap Optimization in HFinFET in Presence of Interface Traps

Physics – Condensed Matter – Mesoscale and Nanoscale Physics

Scientific paper

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

5 pages, 8 figures; Accepted in IEEE Transactions on Nanotechnology

Scientific paper

In this work, using 3D device simulation, we perform an extensive gate to source/drain underlap optimization for the recently proposed hybrid transistor, HFinFET, to show that the underlap lengths can be suitably tuned to improve the on-off ratio as well as the subthreshold characteristics in an ultra-short channel n-type device without significant on performance degradation. We also show that the underlap knob can be tuned to mitigate the device quality degradation in presence of interface traps. The obtained results are shown to be very promising when compared against ITRS 2009 performance projections as well as published state of the art planar and non-planar Silicon MOSFET data of comparable gate lengths using standard benchmarking techniques.

No associations

LandOfFree

Say what you really think

Search LandOfFree.com for scientists and scientific papers. Rate them and share your experience with other people.

Rating

Underlap Optimization in HFinFET in Presence of Interface Traps does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.

If you have personal experience with Underlap Optimization in HFinFET in Presence of Interface Traps, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Underlap Optimization in HFinFET in Presence of Interface Traps will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFWR-SCP-O-217

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.