Computer Science – Hardware Architecture
Scientist
Computer Science
Hardware Architecture
Scientist
A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture
A Novel VLSI Architecture of Fixed-complexity Sphere Decoder
Decoding the Golden Code: a VLSI design
Improving Network-on-Chip-based turbo decoder architectures
Testing Logic Cores using a BIST P1500 Compliant Approach: A Case of Study
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