Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

Details Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET Scalability of spin FPGA: A Reconfigurable Architecture based on spin MOSFET

2011-04-08

arxiv.org/abs/1104.1493v1

J. Appl. Phys. 109, 07C312 (2011)

Physics

Condensed Matter

Mesoscale and Nanoscale Physics

3 pages, 7 figures

Scientific paper

10.1063/1.3537923

Scalability of Field Programmable Gate Array (FPGA) using spin MOSFET (spin FPGA) with magnetocurrent (MC) ratio in the range of 100% to 1000% is discussed for the first time. Area and speed of million-gate spin FPGA are numerically benchmarked with CMOS FPGA for 22nm, 32nm and 45nm technologies including 20% transistor size variation. We show that area is reduced and speed is increased in spin FPGA owing to the nonvolatile memory function of spin MOSFET.

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