Overlapping-gate architecture for silicon Hall bar MOSFET devices in the low electron density and high magnetic field regime

Details Overlapping-gate architecture for silicon Hall bar MOSFET devices in the low electron density and high magnetic field regime Overlapping-gate architecture for silicon Hall bar MOSFET devices in the low electron density and high magnetic field regime

2011-10-07

arxiv.org/abs/1110.1418v1

Materials Science Forum Vol. 700, Advanced Materials and Nanotechnology (AMN-5), 2011 conference on, 93-95 (2012)

Physics

Condensed Matter

Mesoscale and Nanoscale Physics

3 pages

Scientific paper

10.4028/www.scientific.net/MSF.7

A common issue in low temperature measurements of enhancement-mode metal-oxide-semiconductor (MOS) field-effect transistors (FETs) in the low electron density regime is the high contact resistance dominating the device impedance. In that case a voltage bias applied across the source and drain contact of a Hall bar MOSFET will mostly fall across the contacts (and not across the channel) and therefore magneto-transport measurements become challenging. However, from a physical point of view, the study of MOSFET nanostructures in the low electron density regime is very interesting (impurity limited mobility [1], carrier interactions [2,3] and spin-dependent transport [4]) and it is therefore important to come up with solutions [5,6] that work around the problem of a high contact resistance in such devices (c.f. Fig. 1 (a)).

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