Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs

Details Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs Interface Trap Density Metrology of state-of-the-art undoped Si n-FinFETs

2010-11-11

arxiv.org/abs/1011.2582v1

Physics

Condensed Matter

Mesoscale and Nanoscale Physics

9 pages, 4 figures, *G.C.T. and A.P. contributed equally to this work

Scientific paper

The presence of interface states at the MOS interface is a well-known cause of device degradation. This is particularly true for ultra-scaled FinFET geometries where the presence of a few traps can strongly influence device behavior. Typical methods for interface trap density (Dit) measurements are not performed on ultimate devices, but on custom designed structures. We present the first set of methods that allow direct estimation of Dit in state-of-the-art FinFETs, addressing a critical industry need.

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