Extended-p+ Stepped Gate (ESG) LDMOS for Improved Performance

Details Extended-p+ Stepped Gate (ESG) LDMOS for Improved Performance Extended-p+ Stepped Gate (ESG) LDMOS for Improved Performance

2010-08-17

arxiv.org/abs/1008.2835v1

IEEE Trans. on Electron Devices, Vol.57, pp.1719 - 1724, July 2010

Physics

Condensed Matter

Mesoscale and Nanoscale Physics

Journal Paper

Scientific paper

In this paper, we propose a new Extended-p+ Stepped Gate (ESG) thin film SOI LDMOS with an extended-p+ region beneath the source and a stepped gate structure in the drift region of the LDMOS. The hole current generated due to impact ionization is now collected from an n+p+ junction instead of an n+p junction thus delaying the parasitic BJT action. The stepped gate structure enhances RESURF in the drift region, and minimizes the gate-drain capacitance. Based on two-dimensional simulation results, we show that the ESG LDMOS exhibits approximately 63% improvement in breakdown voltage, 38% improvement in on-resistance, 11% improvement in peak transconductance, 18% improvement in switching speed and 63% reduction in gate-drain charge density compared with the conventional LDMOS with a field plate.

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