Physics – Condensed Matter – Materials Science
Scientific paper
2010-02-03
Nature Nanotechnology 5, 727 (2010)
Physics
Condensed Matter
Materials Science
13 pages, 5 figures
Scientific paper
Realization of post-CMOS graphene electronics requires production of semiconducting graphene, which has been a labor-intensive process. We present tailoring of silicon carbide crystals via conventional photolithography and microelectronics processing to enable templated graphene growth on 4H-SiC{1-10n} (n = 8) crystal facets rather than the customary {0001} planes. This allows self-organized growth of graphene nanoribbons with dimensions defined by those of the facet. Preferential growth is confirmed by Raman spectroscopy and high-resolution transmission electron microscopy (HRTEM) measurements, and electrical characterization of prototypic graphene devices is presented. Fabrication of > 10,000 top-gated graphene transistors on a 0.24 cm2 SiC chip demonstrates scalability of this process and represents the highest density of graphene devices reported to date.
Berger Clemens
de Heer Walt. A.
Hankinson John
Hu Yan
Madiomanana Nerasoa K.
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