Cell Architecture for Nanoelectronic Design

Details Cell Architecture for Nanoelectronic Design Cell Architecture for Nanoelectronic Design

2007-08-10

arxiv.org/abs/0708.1454v1

Dans European Nano Systems Worshop - ENS 2006, Paris : France (2006)

Physics

Condensed Matter

Materials Science

Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions)

Scientific paper

Several nanoelectronic devices have been already proved. However, no architecture which makes use of them provides a feasible opportunity to build medium/large systems. Nanoarchitecture proposals only solve a small part of the problems needed to achieve a real design. In this paper, we propose and analyze a cell architecture that overcomes most of those at the gate level. Using the cell structure we build 2 and 3-input NAND gates showing their error probabilities. Finally, we outline a method to further improve the structure's tolerance by taking advantage of interferences among nanodevices. Using this improvement we show that it is possible to reduce the output standard deviation by a factor larger than $\sqrt{2}$ and restitute the signal levels using nanodevices.

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