Analytic model for the surface potential and drain current in negative capacitance field-effect transistors

Details Analytic model for the surface potential and drain current in negative capacitance field-effect transistors Analytic model for the surface potential and drain current in negative capacitance field-effect transistors

2010-03-31

arxiv.org/abs/1004.0015v1

IEEE Transactions on Electron Devices, vol. 57, issue 10, pp. 2405-2409 (2010)

Physics

Condensed Matter

Mesoscale and Nanoscale Physics

9 pages, 6 figures

Scientific paper

10.1109/TED.2010.2062188

In 2008, Salahuddin and Datta proposed that a ferroelectric material operating in the negative capacitance region could act as a step-up converter of the surface potential in a MOS structure, opening a new route for the realization of transistors with steeper subthreshold characteristics (S<60 mV/decade). In this letter, a comprehensive physics-based surface potential and drain current model for the negative capacitance field-effect transistor is reported. The model is aimed to evaluate the potentiality of such transistors for low-power switching applications. Moreover it provides a model core for memories devices relying on the hysteretic behavior of the ferroelectric gate insulator.

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