Shrinking limits of silicon MOSFET's: Numerical study of 10-nm-scale devices

Details Shrinking limits of silicon MOSFET's: Numerical study of 10-nm-scale devices Shrinking limits of silicon MOSFET's: Numerical study of 10-nm-scale devices

1999-10-17

arxiv.org/abs/cond-mat/9910258v1

Physics

Condensed Matter

Mesoscale and Nanoscale Physics

8 pages, 10 figures. Submitted to Special Issue of Superlattices and Microstructures: Third NASA Workshop on Device Modeling,

Scientific paper

10.1006/spmi.1999.0807

We have performed numerical modeling of dual-gate ballistic n-MOSFET's with channel length of the order of 10 nm, including the effects of quantum tunneling along the channel and through the gate oxide. Our analysis includes a self-consistent solution of the full (two-dimensional) electrostatic problem, with account of electric field penetration into the heavily-doped electrodes. The results show that transistors with channel length as small as 8 nm can exhibit either a transconductance up to 4,000 mS/mm or gate modulation of current by more than 8 orders of magnitude, depending on the gate oxide thickness. These characteristics make the devices satisfactory for logic and memory applications, respectively, though their gate threshold voltage is rather sensitive to nanometer-scale variations in the channel length.

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