On the Bandstructure Velocity and Ballistic Current of Ultra Narrow Silicon Nanowire Transistors as a Function of Cross Section Size, Orientation and Bias

Details On the Bandstructure Velocity and Ballistic Current of Ultra Narrow Silicon Nanowire Transistors as a Function of Cross Section Size, Orientation and Bias On the Bandstructure Velocity and Ballistic Current of Ultra Narrow Silicon Nanowire Transistors as a Function of Cross Section Size, Orientation and Bias

2010-06-21

arxiv.org/abs/1006.4174v1

Journal of Applied Physics, vol. 107, p. 113701, 2010

Physics

Condensed Matter

Mesoscale and Nanoscale Physics

31 pages, 7 figures, 1 table

Scientific paper

10.1063/1.3372764

A 20 band sp3d5s* spin-orbit-coupled, semi-empirical, atomistic tight-binding (TB) model is used with a semi-classical, ballistic, field-effect-transistor (FET) model, to theoretically examine the bandstructure carrier velocity and ballistic current in silicon nanowire (NW) transistors. Infinitely long, uniform, cylindrical and rectangular NWs, of cross sectional diameters/sides ranging from 3nm to 12nm are considered. For a comprehensive analysis, n-type and p-type metal-oxide-semiconductor (NMOS and PMOS) NWs in [100], [110] and [111] transport orientations are examined. In general, physical cross section reduction increases velocities, either by lifting the heavy mass valleys, or significantly changing the curvature of the bands. The carrier velocities of PMOS [110] and [111] NWs are a strong function of diameter, with the narrower D=3nm wires having twice the velocities of the D=12nm NWs. The velocity in the rest of the NW categories shows only minor diameter dependence. This behavior is explained through features in the electronic structure of the silicon host material. The ballistic current, on the other hand, shows the least sensitivity with cross section in the cases where the velocity has large variations. Since the carrier velocity is a measure of the effective mass and reflects on the channel mobility, these results can provide insight into the design of NW devices with enhanced performance and performance tolerant to structure geometry variations. In the case of ballistic transport in high performance devices, the [110] NWs are the ones with both high NMOS and PMOS performance, as well as low on-current variations with cross section geometry variations.

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