Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format

Details Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format

2006-09-08

arxiv.org/abs/cs/0609036v1

Computer Science

Hardware Architecture

6 Pages;Published in Proceedings of the 11th International CSI Computer Conference (CSICC'06), Tehran, Jan 24-26, 2006, pp.59-

Scientific paper

IEEE 754r is the ongoing revision to the IEEE 754 floating point standard and a major enhancement to the standard is the addition of decimal format. Firstly, this paper proposes novel two transistor AND and OR gates. The proposed AND gate has no power supply, thus it can be referred as the Powerless AND gate. Similarly, the proposed two transistor OR gate has no ground and can be referred as Groundless OR. Secondly for IEEE 754r format, two novel BCD adders called carry skip and carry look-ahead BCD adders are also proposed in this paper. In order to design the carry look-ahead BCD adder, a novel 4 bit carry look-ahead adder called NCLA is proposed which forms the basic building block of the proposed carry look-ahead BCD adder. Finally, the proposed two transistors AND and OR gates are used to provide the optimized small area low power high throughput circuitries of the proposed BCD adders.

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