Computer Science – Hardware Architecture
Scientific paper
May 2007
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2007spie.6356e..45r&link_type=abstract
Eighth International Conference on Quality Control by Artificial Vision. Edited by Fofi, David; Meriaudeau, Fabrice. Proceedin
Computer Science
Hardware Architecture
Scientific paper
The starting point for all successful system development is the simulation. Performing high level simulation of a system can help to identify, insolate and fix design problems. This work presents Uranus, a software tool for simulation and evaluation of image processing algorithms with support to migrate them to an FPGA environment for algorithm acceleration and embedded processes purposes. The tool includes an integrated library of previous coded operators in software and provides the necessary support to read and display image sequences as well as video files. The user can use the previous compiled soft-operators in a high level process chain, and code his own operators. Additional to the prototyping tool, Uranus offers FPGA-based hardware architecture with the same organization as the software prototyping part. The hardware architecture contains a library of FPGA IP cores for image processing that are connected with a PowerPC based system. The Uranus environment is intended for rapid prototyping of machine vision and the migration to FPGA accelerator platform, and it is distributed for academic purposes.
Arias-Estrada M.
Castillo-Jimenez Liz
Rosales-Hernández Victor
Treviño Torres Abel
Viveros-Velez Gilberto
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