Statistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions

Details Statistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions Statistical Yield Modeling for IC Manufacture: Hierarchical Fault Distributions

2003-03-10

arxiv.org/abs/physics/0303039v1

Russian Microelectronics, 2003, V.32, N 1, P. 51

Physics

Data Analysis, Statistics and Probability

OAO Angstrem, Moscow Institute of Electronic Engineering (Technical University), Moscow, Russia, 19 pages, 2 figures

Scientific paper

A hierarchical approach to the construction of compound distributions for process-induced faults in IC manufacture is proposed. Within this framework, the negative binomial distribution and the compound binomial distribution are treated as level-1 models. The hierarchical approach to fault distribution offers an integrated picture of how fault density varies from region to region within a wafer, from wafer to wafer within a batch, and so on. A theory of compound-distribution hierarchies is developed by means of generating functions. With respect to applications, hierarchies of yield means and yield probability-density functions are considered and an in-process measure of yield loss is introduced. It is shown that the hierarchical approach naturally embraces the Bayesian approach.

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