Plans for PANDA Online Computing

Details Plans for PANDA Online Computing Plans for PANDA Online Computing

2009-10-09

arxiv.org/abs/0910.1682v2

JINST 4:P11001,2009

Physics

Instrumentation and Detectors

presented at Workshop on Fast Cerenkov Detectors, May 11-13, 2009, Giessen, Germany, 9 pages, 3 figures, accepted for publicat

Scientific paper

10.1088/1748-0221/4/11/P11001

The PANDA experiment will not use any hardware trigger, i.e. all raw data are streaming in the data acquisition with a bandwidth of ~280 GB/s. The PANDA Online System is designed to perform data reduction by a factor of ~800 by reconstruction algorithms programmed in VHDL (Very High Speed Integrated Circuit Hardware Description Language) on FPGAs (Field Programmable Gate Arrays).

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