Optimizing scanning array performance using gain normalization and timedelay and integrate pixel deselection during readout, hybrid, and focal plane testing

Details Optimizing scanning array performance using gain normalization and timedelay and integrate pixel deselection during readout, hybrid, and focal plane testing Optimizing scanning array performance using gain normalization and timedelay and integrate pixel deselection during readout, hybrid, and focal plane testing

Jul 1992

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1992spie.1686..188a&link_type=abstract

Proc. SPIE Vol. 1686, p. 188-203, Test and Evaluation of Infrared Detectors and Arrays II, Forney M. Hoke; Ed.

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Scientific paper

When testing infrared readouts, detector-readout hybrid assemblies, or focal plane arrays (FPAs), performance optimization is usually limited to adjustment of biases or clock rails, or subtle changes in readout timing. These generally result in global changes to the characteristics of the entire array rather than affecting individual pixels and channels. Using a scanning system that incorporates per channel gain normalization and a redundant time delay and integrate (TDI) architecture in the readout, pixels can be enhanced or deselected using an on- chip static RAM according to user-defined criteria resulting in improved uniformity of performance. A series of tests can be run automatically that evaluate each pixel's behavior at the readout or the hybrid level. When compared to or compiled against array-wide averages or system specifications, a map of dead or degraded pixels is created, and the timing necessary to either normalize each channel from a gain standpoint or mask out individual pixels is applied to the device under test. This technique has been successfully applied to 480 X 6 (120 X 4 X 6 in TDI) scanning architectures in both InSb and HgCdTe systems as well as multiple-chip and dual-band configurations. This paper describes a methodology and details how readout devices were screened and selected for hybridization and FPA build. The chip architecture and control timing is discussed to show how normalization and deselection was accomplished with a minimum of clock lines involved. A software utility is presented that allowed easy graphical interface to the user for manipulating the functions of the device. Algorithms for optimizing performance are then discussed and evaluated. Trade-offs made in optimizing one parameter against another are analyzed. Finally, results are presented demonstrating improved performance, customized by pixel to suit application specifications.

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