New-generation CCD controller requirements and an example: the San Diego State University generation II controller

Details New-generation CCD controller requirements and an example: the San Diego State University generation II controller New-generation CCD controller requirements and an example: the San Diego State University generation II controller

Jul 1998

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1998spie.3355..512l&link_type=abstract

Proc. SPIE Vol. 3355, p. 512-519, Optical Astronomical Instrumentation, Sandro D'Odorico; Ed.

Physics

Optics

8

Scientific paper

New generation astronomical CCD controllers are being required to operate a variety of CCDs in a range of ground-based applications. These include simultaneous readout from two or four corners of the same CCD (multiple readout), operation of several CCDs in the same focal plane (mosaics), fast readout of small devices for wavefront sensing in adaptive optics systems, readout of only a small region or number of regions of a single CCD (sub-image or region of interest readout), merging the charge from neighboring pixels before readout (binning), continuous readout of devices for drift scan observations, and low contrast polarimetric or spectroscopic differential imaging. Most astronomical applications require that the controller electronics not contribute significantly to the readout noise of the CCD, that the dynamic range of the CCD be fully sampled, that the CCD be read out as quickly as possible from one or more readout channels, and that some flexibility in readout modes and device format exist. A further requirement imposed by some institutions is that a single controller design be used for all their CCD instruments to minimize maintenance and development efforts. The Generation II controller design recently completed at San Diego State University to address these requirements is reviewed. A user-programmable digital signal processor (DSP) operating as a sequencer and communications processor is combined with 12-bit digital-to-analog converters for setting all CCD voltages, a video processor chain with speeds of up to 1 MHz, 16-bit analog-to-digital converters, and a bussed backplane architecture for incorporating the control and readout of multiple CCDs by replicating the clock driver and video processing elements.

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