Computer Science – Hardware Architecture
Scientific paper
2011-09-04
Computer Science
Hardware Architecture
4 pages, 4 figures, IEEE 2010 Second Pacific-Asia Conference on Circuits, Communications and System (PACCS)
Scientific paper
Networks-on-Chip (NoCs) for future many-core processor platforms integrate more and more heterogeneous components of different types and many real-time and latency-sensitive applications can run on a single chip concurrently. The reconfigurable FPGA and reconfigurable NoCs have emerged for the purpose of reusability. Those types' traffics within NoCs exhibit diverse, burst, and unpredictable communication patterns. QoS guaranteed mechanisms are necessary to provide guaranteed throughput (GT) or guaranteed bandwidth (GB) performance for NoCs. In this paper, we propose a QoS routing algorithm inspired by bees' foraging behaviors to provide guaranteed bandwidth performance. Virtual circuits and Spatial Division Multiplexing are employed to maintain available paths for different type's traffics.
Gu Huaxi
Xie Peibo
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