Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques

Computer Science – Hardware Architecture

Scientific paper

Rate now

  [ 0.00 ] – not rated yet Voters 0   Comments 0

Details

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

A new approach for enhancing the process-variation tolerance of digital circuits is described. We extend recent advances in statistical timing analysis into an optimization framework. Our objective is to reduce the performance variance of a technology-mapped circuit where delays across elements are represented by random variables which capture the manufacturing variations. We introduce the notion of statistical critical paths, which account for both means and variances of performance variation. An optimization engine is used to size gates with a goal of reducing the timing variance along the statistical critical paths. We apply a pair of nested statistical analysis methods deploying a slower more accurate approach for tracking statistical critical paths and a fast engine for evaluation of gate size assignments. We derive a new approximation for the max operation on random variables which is deployed for the faster inner engine. Circuit optimization is carried out using a gain-based algorithm that terminates when constraints are satisfied or no further improvements can be made. We show optimization results that demonstrate an average of 72% reduction in performance variation at the expense of average 20% increase in design area.

No associations

LandOfFree

Say what you really think

Search LandOfFree.com for scientists and scientific papers. Rate them and share your experience with other people.

Rating

Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.

If you have personal experience with Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Improving the Process-Variation Tolerance of Digital Circuits Using Gate Sizing and Statistical Techniques will most certainly appreciate the feedback.

Rate now

     

Profile ID: LFWR-SCP-O-431937

  Search
All data on this website is collected from public sources. Our data reflects the most accurate information available at the time of publication.