Implementation of mean-timing and subsequent logic functions on an FPGA

Details Implementation of mean-timing and subsequent logic functions on an FPGA Implementation of mean-timing and subsequent logic functions on an FPGA

2011-09-22

arxiv.org/abs/1109.4735v2

Physics

Instrumentation and Detectors

15 pages, 11 figures

Scientific paper

10.1016/j.nima.2011.12.104

This article describes the implementation of a mean-timer and coincidence
logic on a Virtex-5 FPGA for trigger purposes in a particle physics experiment.
The novel feature is that the mean-timing and the coincidence logic are not
synchronized with a clock which allows for a higher resolution of approximately
400 ps, not limited by a clock frequency.

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