Gate-level simulation of logical state preparation

Details Gate-level simulation of logical state preparation Gate-level simulation of logical state preparation

2006-08-14

arxiv.org/abs/quant-ph/0608112v1

Physics

Quantum Physics

8 pages, 2 figures

Scientific paper

Quantum error correction and fault-tolerant quantum computation are two fundamental concepts which make quantum computing feasible. While providing a theoretical means with which to ensure the arbitrary accuracy of any quantum circuit, fault-tolerant error correction is predicated upon the robust preparation of logical states. An optimal direct circuit and a more complex fault-tolerant circuit for the preparation of the [[7,1,3]] Steane logical-zero are simulated in the presence of discrete quantum errors to quantify the regime within which fault-tolerant preparation of logical states is preferred.

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