Computer Science – Hardware Architecture
Scientific paper
Oct 2004
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2004spie.5578..410a&link_type=abstract
Photonics North 2004: Optical Components and Devices. Edited by Armitage, John C.; Fafard, Simon; Lessard, Roger A.; Lampropoul
Computer Science
Hardware Architecture
Scientific paper
A general purpose FPGA architecture for real-time thresholding is proposed in this paper. The hardware architecture is based on a weight-based clustering threshold algorithm that takes the thresholding as a problem of clustering background and foreground pixels. This method employs the clustering capability of a two-weight neural network to find the centriods of the two pixel groups. The image threshold is the average of these two centriods. The proposed method is an adaptive thresholding technique because for every input pixel the closest weight is selected for updating. Updating is based on the difference between the input pixel gray level and the associated weight, scaled by a learning rate factor. The hardware system is implemented on a FPGA platform and consists of two functional blocks. The first block is obtaining the threshold value for the image frame, another block applies the threshold value to the frame. This parallelism and the simple hardware component of both blocks make this approach suitable for real-time applications, while the performance remains comparable with the Otsu technique frequently used in off-line threshold determination. Results from the proposed algorithm are presented for numerous examples, both from simulations and experimentally using the FPGA. Although the primary application of this work is to centroiding of laser spots, its use in other applications will be discussed.
Ashari Elham
Hornsey Richard I.
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