Faster Energy Efficient Dadda Based Baugh-Wooley Multipliers

Details Faster Energy Efficient Dadda Based Baugh-Wooley Multipliers Faster Energy Efficient Dadda Based Baugh-Wooley Multipliers

2011-10-14

arxiv.org/abs/1110.3281v4

Computer Science

Hardware Architecture

Scientific paper

In this work faster Baugh-Wooley multiplication has been achieved by using a combination of two design techniques: partition of the partial products into two parts for independent parallel column compression and acceleration of the final addition using a hybrid adder proposed in this work. Based on the proposed techniques 8, 16, 32 and 64-bit Dadda based Baugh-Wooley multipliers has been developed and compared with the regular Baugh-Wooley multiplier. The performance of the proposed multiplier is analyzed by evaluating the delay, area and power, with 180 nm process technologies on interconnect and layout using industry standard design and layout tools. The result analysis shows that the 64-bit proposed multiplier is as much as 26.9% faster than the regular Baugh-Wooley multiplier and requires only 2.21% more power. Also the power-delay product of the proposed design is significantly lower than that of the regular Baugh-Wooley multiplier.

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