Development of the large-area silicon PIN diode with 2 millimeter-thick depletion layer for hard x-ray detector (HXD) on board ASTRO-E

Details Development of the large-area silicon PIN diode with 2 millimeter-thick depletion layer for hard x-ray detector (HXD) on board ASTRO-E Development of the large-area silicon PIN diode with 2 millimeter-thick depletion layer for hard x-ray detector (HXD) on board ASTRO-E

Jul 1997

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1997spie.3115..244s&link_type=abstract

Proc. SPIE Vol. 3115, p. 244-253, Hard X-Ray and Gamma-Ray Detector Physics, Optics, and Applications, Richard B. Hoover; F. Pat

Physics

Optics

1

Scientific paper

ASTRO-E is the next Japanese x-ray satellite to be launched in the year 2000. It carries three high-energy astrophysical experiments, including the hard x-ray detector (HXD) which is unique in covering the wide energy band from 10 keV to 700 keV with an extremely low background. The HXD is a compound-eye detector, employing 16 GSO/BGO well-type phoswich scintillation counters together with 64 silicon PIN detectors. The scintillation counters cover an energy range of 40 - 700 keV, while the PIN diodes fill the intermediate energy range from 10 keV to 70 keV with an energy resolution about 3 keV. In this paper, we report on the developments of the large area, thick silicon PIN diodes. In order to achieve a high quantum efficiency up to 70 keV with a high energy resolution, we utilize a double stack of silicon PIN diodes, each 20 by 20 mm(superscript 2) in size and 2 mm thick. Signals from the two diodes are summed into a single output. Four of these stacks (or eight diodes) are placed inside the deep BGO active-shield well of a phoswich counter, to achieve an extremely low background environment. Thus, the HXD utilizes 64 stacked silicon PIN detectors, achieving a total geometrical collecting area of 256 cm(superscript 2). We have developed the 2 mm thick silicon PIN diodes which have low leakage current, a low capacitance, and a high breakdown voltage to meet the requirements of our goal. Through various trials in fabricating PIN diodes with different structures, we have found optimal design parameters, such as mask design of the surface p(superscript +) layer and the implantation process.

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