Physics
Scientific paper
Jul 2003
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2003icrc....6.3461y&link_type=abstract
Proceedings of the 28th International Cosmic Ray Conference. July 31-August 7, 2003. Trukuba, Japan. Under the auspices of the I
Physics
Scientific paper
A prototype multi-directional muon detector has been in operation at Sao ˜ Martinho in Brazil, since March, 2001. We now plan to extend the detector in size to a full scale detector comparable to the Nagoya muon telescope. We have started to design a new recording system using the FPGA and VHDL. By using the FPGA and VHDL, it becomes possible to design a more complicated and advanced logical circuit at a reduced cost. As the result, we can determine the incident direction of every single muon and record the count rates in the total 121 incident directions. It is also noted that the power consumption can be decreased drastically. 2. Introduction We have installed the prototype multi-directional muon telescope at the INPE's Southern Space Observatory (Geographic Lat: 29.44° S, Long: 53.81° W, Alt: 500 m) at Sao Martinho in Brazil, on March, 2001 [1]. It is confirmed that ˜ the pitch angle coverage of the network is greatly improved by this new detector in Brazil [1,2], because the former network consisting of Nagoya, Hobart and Mawson had a big gap in directional coverage over the Atlantic and Europ ean region, and this gap was filled by the new detector in Brazil [3]. It is concluded, however, that the extension of the Brazilian detector in size is required for more precise and reliable observations [1]. We are now planning to extend the detector size to a full scale size comparable to the Nagoya muon telescope (6×6 array of 1 m2 detectors). We have started to design a new recording system using the devices of Field Programmable Gate Array (FPGA) and VHSIS Hardware Description Language (VHDL) for the full-scale muon telescope. By using the FPGA and VHDL, it becomes possible to design a more complicated and advanced logical circuit at a reduced cost, which could not be accomplished by the conventional system using the logic gate ICs.
Akahane Shigenobu
Bieber John W.
Evenson Paul
Fujii Zenjiro
Kato Chihiro
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