Design and analysis of real-time wavefront processor

Details Design and analysis of real-time wavefront processor Design and analysis of real-time wavefront processor

Dec 2004

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2004spie.5639..193z&link_type=abstract

Adaptive Optics and Applications III. Edited by Jiang, Wenhan; Suzuki, Yoshiji. Proceedings of the SPIE, Volume 5639, pp. 193-

Physics

Optics

Scientific paper

Latency of wavefront processor is an important factor of closed loop adaptive optical systems. For an adaptive optical system using Shack-Hartmann wave-front sensing and point beam, by ways of task queue, subtask arithmetic decomposition and subtask structure design, a multi-processors structure based on moder parallelism theory is built to realize a pipeline of wavefront gradient, wavefront reconstruction and wavefront control. By traits of field programmable gate array(FPGA) and digital signal processor(DSP), a pipeline wavefront processor based on FPGA+DSP structure is built with highly real-time performance. Clocks of FPGA and DSP, "age" of correctors are primary sources of this wavefront processor"s latency. For a 61-element adaptive optical system whose sampling frequency is 2900HZ, latency of this wavefront processor is less than 100us.

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