Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs

Details Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs

2007-10-25

arxiv.org/abs/0710.4644v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping system consisting of a VLIW processor and FPGAs. The generated code is annotated with information that triggers cycle generation for the hardware in parallel to the execution of the translated program. The VLIW processor executes the translated program whereas the FPGAs contain the hardware for the parallel cycle generation and the bus interface that adapts the bus of the VLIW processor to the SoC bus of the emulated processor core.

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