Clock and Trigger Synchronization between Several Chassis of Digital Data Acquisition Modules

Details Clock and Trigger Synchronization between Several Chassis of Digital Data Acquisition Modules Clock and Trigger Synchronization between Several Chassis of Digital Data Acquisition Modules

2007-01-09

arxiv.org/abs/nucl-ex/0701016v1

Physics

Nuclear Physics

Nuclear Experiment

CAARI 2006

Scientific paper

10.1016/j.nimb.2007.04.181

In applications with segmented high purity Ge detectors or other detector arrays with tens or hundreds of channels, where the high development cost and limited flexibility of application specific integrated circuits outweigh their benefits of low power and small size, the readout electronics typically consist of multi-channel data acquisition modules in a common chassis for power, clock and trigger distribution, and data readout. As arrays become larger and reach several hundred channels, the readout electronics have to be divided over several chassis, but still must maintain precise synchronization of clocks and trigger signals across all channels. This division becomes necessary not only because of limits given by the instrumentation standards on module size and chassis slot numbers, but also because data readout times increase when more modules share the same data bus and because power requirements approach the limits of readily available power supplies. In this paper, we present a method for distributing clocks and triggers between 4 PXI chassis containing DGF Pixie-16 modules with up to 226 acquisition channels per chassis in a data acquisition system intended to instrument the over 600 channels of the SeGA detector array at the National Superconducting Cyclotron Laboratory. Our solution is designed to achieve synchronous acquisition of detector waveforms from all channels with a jitter of less then 1 ns, and can be extended to a larger number of chassis if desired.

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