Circuit design approaches for improved radiation hardness

Details Circuit design approaches for improved radiation hardness Circuit design approaches for improved radiation hardness

Jun 1994

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1994spie.2226..135m&link_type=abstract

Proc. SPIE Vol. 2226, p. 135-141, Infrared Readout Electronics II, Eric R. Fossum; Ed.

Physics

Scientific paper

The use of a multiple dielectric gate insulator, and the addition of a gate insulator extension and guard-bars to the NMOS transistors, has resulted in a significant increase in total-dose ionizing radiation resistance for CMOS IR readout multiplexer circuits operating at cryogenic temperatures. This paper describes the implementation of these modifications, and also some observed anomalous transistor offset voltages that were apparently due to charges trapped in the multiple dielectric gate insulator during the circuit fabrication process.

Affiliated with

Also associated with

No associations

Rating

Circuit design approaches for improved radiation hardness does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.

If you have personal experience with Circuit design approaches for improved radiation hardness, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit design approaches for improved radiation hardness will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFWR-SCP-O-1509645