Assessing Random Dynamical Network Architectures for Nanoelectronics

Details Assessing Random Dynamical Network Architectures for Nanoelectronics Assessing Random Dynamical Network Architectures for Nanoelectronics

2008-05-17

arxiv.org/abs/0805.2684v1

Computer Science

Hardware Architecture

8 pages, 6 figures, IEEE/ACM Symposium on Nanoscale Architectures, NANOARCH 2008, Anaheim, CA, USA, Jun 12-13, 2008

Scientific paper

Independent of the technology, it is generally expected that future nanoscale devices will be built from vast numbers of densely arranged devices that exhibit high failure rates. Other than that, there is little consensus on what type of technology and computing architecture holds most promises to go far beyond today's top-down engineered silicon devices. Cellular automata (CA) have been proposed in the past as a possible class of architectures to the von Neumann computing architecture, which is not generally well suited for future parallel and fine-grained nanoscale electronics. While the top-down engineered semi-conducting technology favors regular and locally interconnected structures, future bottom-up self-assembled devices tend to have irregular structures because of the current lack precise control over these processes. In this paper, we will assess random dynamical networks, namely Random Boolean Networks (RBNs) and Random Threshold Networks (RTNs), as alternative computing architectures and models for future information processing devices. We will illustrate that--from a theoretical perspective--they offer superior properties over classical CA-based architectures, such as inherent robustness as the system scales up, more efficient information processing capabilities, and manufacturing benefits for bottom-up designed devices, which motivates this investigation. We will present recent results on the dynamic behavior and robustness of such random dynamical networks while also including manufacturing issues in the assessment.

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