Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

Details Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction Area-Efficient Selective Multi-Threshold CMOS Design Methodology for Standby Leakage Power Reduction

2007-10-25

arxiv.org/abs/0710.4762v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

This paper presents a design flow for an improved selective
multi-threshold(Selective-MT) circuit. The Selective-MT circuit is improved so
that plural MT-cells can share one switch transistor. We propose the design
methodology from RTL(Register Transfer Level) to final layout with optimizing
switch transistor structure.

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