Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

Details Analog and Digital Circuit Design in 65 nm CMOS: End of the Road? Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

2007-10-25

arxiv.org/abs/0710.4709v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog blocks. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.

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