An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs

Details An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs

2007-10-25

arxiv.org/abs/0710.4706v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Hardware Architecture

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

This paper presents an infrastructure to test the functionality of the specific architectures output by a high-level compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to Field-Programmable Gate Array (FPGA) platforms is concerned.

Affiliated with

Also associated with

No associations

Rating

An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs does not yet have a rating. At this time, there are no reviews or comments for this scientific paper.

If you have personal experience with An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFWR-SCP-O-431900