An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs

Details An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs An Infrastructure to Functionally Test Designs Generated by Compilers Targeting FPGAs

Publishing date

2007-10-25

URL

arxiv.org/abs/0710.4706v1

Journals

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Science

Computer Science

Field

Hardware Architecture

Additional info

Submitted on behalf of EDAA (http://www.edaa.com/)

Type

Scientific paper

Abstract

This paper presents an infrastructure to test the functionality of the specific architectures output by a high-level compiler targeting dynamically reconfigurable hardware. It results in a suitable scheme to verify the architectures generated by the compiler, each time new optimization techniques are included or changes in the compiler are performed. We believe this kind of infrastructure is important to verify, by functional simulation, further research techniques, as far as compilation to Field-Programmable Gate Array (FPGA) platforms is concerned.

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