An FPGA-based Torus Communication Network

Details An FPGA-based Torus Communication Network An FPGA-based Torus Communication Network

2011-02-11

arxiv.org/abs/1102.2346v1

PoS LATTICE2010:038,2010

Physics

High Energy Physics

High Energy Physics - Lattice

7 pages, 3 figures, proceedings of the XXVIII International Symposium on Lattice Field Theory, Lattice2010, June 14-19, 2010,

Scientific paper

We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results.

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