Computer Science – Robotics
Scientific paper
Mar 1992
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1992spie.1612...49d&link_type=abstract
Proc. SPIE Vol. 1612, p. 49-54, Cooperative Intelligent Robotics in Space II, William E. Stoney; Ed.
Computer Science
Robotics
Scientific paper
This paper surveys past architectures accommodating autonomy and projects future directions in these architectures. In recent years research toward autonomous systems has been stimulated by Space Station Freedom, SDI, and DARPA's Strategic Computing Initiative. More recently, the Mars Rover studies and the Human Exploration Initiative are driving the needs for onboard computer systems which provide either autonomous or supervised autonomous operations. While early work focussed on defining functional requirements for such systems and the development of algorithms for each functional element, current research focuses on integrated sensori-motor control and techniques to assure that the processing architectures to execute these onboard functions will respect well-defined volume, weight, and power budgets. The success of programs which demonstrate autonomous systems such as the Martin Marietta Autonomous Land Vehicle, as well as large scale laboratory demonstrations of supervised autonomy, show this can be done. Integration requires many disciplines to be jointly considered: vision, planning, control, computer systems, and platform management. The system engineering discipline to balance the design imperatives of each within a well- engineered solution must advance as well. One of the intriguing aspects of this problem is that the approach and resulting architecture must accommodate changes to the mission and associated key mission timing parameters. Therefore, the ease of evolving both the architecture and mission contribute design imperatives of their own. This paper discusses processing architectures for autonomy and lessons learned in our past work, the impact of emerging techniques such as neural networks, and our recent work to exploit custom hardware to accommodate the increased number and complexity of onboard functions required for autonomous platforms while respecting stringent volume, weight, and power considerations.
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