A parallel analogue-digital photodiode array processor chip with hard-wired morphologic algorithms

Details A parallel analogue-digital photodiode array processor chip with hard-wired morphologic algorithms A parallel analogue-digital photodiode array processor chip with hard-wired morphologic algorithms

Oct 2005

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2005spie.5964..104h&link_type=abstract

Advances in Optical Thin Films II. Edited by Amra, Claude; Kaiser, Norbert; Macleod, H. Angus. Proceedings of the SPIE, Volume

Mathematics

Logic

Scientific paper

We present a chip, which is suited for applications in data-communication areas as well as in image-processing applications. Through the combination of parallel signal gathering and processing, we save components and we can increase the processing rate. We think thereby on problems like pre processing in camera systems also called "intelligent sensor". The chip has a structure as follows. Every processor element contains an optical detector, a trans-impedance amplifier and a comparator. A digital logic is directly connected to these components. This logic realizes the programmable processing of the signals. Each processor element is connected to its four direct orthogonal neighbours within the processor array. The digital parts consist of a special processor. It realises simple hard-wired image algorithms. As an example for cooperation of the analogue and digital part we have implemented some morphologic operations. Our receiver consists of a 8×8 photodiode array. A data rate of 625 Mbit/s for an average optical power in the range of 25 µW to 500 µW is possible for a bit-error-rate of 10-9 per channel. Signal processing limits the frequency to 200 MHz for a processor element according to simulations. Using an image with a size of 6×6 according to parallel data transfer a data throughput of 7.2 GHz results.

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