A Design of Low Frequency Time-Code Receiver Based on DSP and FPGA

Details A Design of Low Frequency Time-Code Receiver Based on DSP and FPGA A Design of Low Frequency Time-Code Receiver Based on DSP and FPGA

Jun 2006

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2006jtf....29...27l&link_type=abstract

Journal of Time and Frequency (ISSN 1001-1544), Vol. 29, No. 1, p. 27 - 34 (2006)

Physics

Lf Time-Code Signal, Digital Receiver, Dsp, Fpga

Scientific paper

The hardware of a low frequency time-code receiver which was designed with FPGA (field programmable gate array) and DSP (digital signal processor) is introduced. The method of realizing the time synchronization for the receiver system is described. The software developed for DSP and FPGA is expounded, and the results of test and simulation are presented. The design is charcterized by high accuracy, good reliability, fair extensibility, etc.

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