Evaluation of cryogenic readout circuits with GaAs JFETs for far-infrared detectors

Details Evaluation of cryogenic readout circuits with GaAs JFETs for far-infrared detectors Evaluation of cryogenic readout circuits with GaAs JFETs for far-infrared detectors

Aug 2000

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2000spie.4008..452o&link_type=abstract

Proc. SPIE Vol. 4008, p. 452-458, Optical and IR Telescope Instrumentation and Detectors, Masanori Iye; Alan F. Moorwood; Eds.

Physics

Instrumentation and Detectors

Scientific paper

The characteristics of gallium arsenide junction field- effect transistors (GaAs JFETs) and the performance of cryogenic readout circuits using GaAs JFETs with various gate sizes ranging form W/L equals 5micrometers /0.5micrometers to 200micrometers /200micrometers to systematically measure their static characteristics and low-frequency noise spectra. We found that the low-frequency noise voltage depends on the device size in the saturation region of GaAs JFETs at 4.2 K, and the power density of the noise voltage is inversely proportional to the gate are. These findings allowed us to determine the Hooge parameter of the GaAs JFET at 4.2 K to be 4 by 10-5, assuming that the carrier mobility is 1.5 by 103 cm2/Vs. On the other hand, we did not find the obvious correlation between the low-frequency noise and gate size in the ohmic region of GaAs JFETs. Based on these measurements for GaAs JFETs, we fabricated and tested a dual GaAs JFET, a source-follower-per-detector (SFD) circuit, and a 20 by 3 channel SFD circuit array. The Common-Mode-Rejection-Ratio (CMRR) of the dual GaAs JFET with W/L equals 50micrometers /20micrometers at 4.2 K was determined to be 40-60 dB under small power dissipation. The performance of SFD circuits and 20 by 3 channel SFD arrays for 2D far-IR Ge:Ga detector readouts are currently being evaluated.

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