Faster and Low Power Twin Precision Multiplier

Details Faster and Low Power Twin Precision Multiplier Faster and Low Power Twin Precision Multiplier

2011-10-15

arxiv.org/abs/1110.3376v2

Computer Science

Hardware Architecture

5 pages, 10 figures and 5 tables

Scientific paper

In this work faster unsigned multiplication has been achieved by using a combination of High Performance Multiplication [HPM] column reduction technique and implementing a N-bit multiplier using 4 N/2-bit multipliers (recursive multiplication) and acceleration of the final addition using a hybrid adder. Low power has been achieved by using clock gating technique. Based on the proposed technique 16 and 32-bit multipliers are developed. The performance of the proposed multiplier is analyzed by evaluating the delay, area and power, with TCBNPHP 90 nm process technology on interconnect and layout using Cadence NC launch, RTL compiler and ENCOUNTER tools. The results show that the 32-bit proposed multiplier is as much as 22% faster, occupies only 3% more area and consumes 30% lesser power with respect to the recently reported twin precision multiplier.

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