Pushing KrF photolithography limit for 3D integrated circuit

Details Pushing KrF photolithography limit for 3D integrated circuit Pushing KrF photolithography limit for 3D integrated circuit

May 2004

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2004spie.5377..997c&link_type=abstract

Optical Microlithography XVII. Edited by Smith, Bruce W. Proceedings of the SPIE, Volume 5377, pp. 997-1004 (2004).

Physics

Scientific paper

In this paper, a study of shrinking a 3-D memory circuit beyond 0.26mm pitch by currently available KrF photolithography tool is described. Line/space patterns and post structures are included in this study due to the architecture of 3-D memory. Resolution capability of various OAI techniques such as annular, QUASAR, and dipole illumination are analyzed by simulation and wafer printing images. Both attenuated and alternating type phase shifting masks are used to test the resolution limit of various memory structures. A new method of making "alternating-type" phase shifting mask for post pattern is presented in this study. This new phase shifting mask provides a great improvement for resolving small post structures, which have limited process window due to 2-D optical interference effect. This study presents an application of KrF RET to 3-D memory circuit by smart circuit design.

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