Noise minimization via deep submicron system-on-chip integration in megapixel CMOS imaging sensors

Details Noise minimization via deep submicron system-on-chip integration in megapixel CMOS imaging sensors Noise minimization via deep submicron system-on-chip integration in megapixel CMOS imaging sensors

Sep 2005

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2005spie.5957....1k&link_type=abstract

Integrated Optics: Theory and Applications. Edited by Pustelny, Tadeusz; Lambeck, Paul V.; Gorecki, Christophe. Proceedings of

Physics

Optics

1

Scientific paper

Infrared sensor designers have long maximized S/N ratio by employing pixel-based amplification in conjunction with supplemental noise suppression. Instead, we suppress photodiode noise using novel SoC implementation with simple three transistor pixel; supporting SoC components include a feedback amplifier having elements distributed amongst the pixel and column buffer, a tapered reset clock waveform, and reset timing generator. The tapered reset method does not swell pixel area, compel processing of the correlated reset and signal values, or require additional memory. Integrated in a 2.1M pixel imager developed for generating high definition television, random noise is ~8e- at video rates to 225MHz. Random noise of ~30e- would otherwise be predicted for the 5μm by 5μm pixels having 5.5fF detector capacitance with negligible image lag. Minimum sensor S/N ratio is 52dB with 1920 by 1080 progressive readout at 60Hz, 72Hz and 90Hz. Fixed pattern noise is <2 DN via on-chip signal processing.

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