Computer Science
Scientific paper
Jul 1991
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1991spie.1447..243k&link_type=abstract
Proc. SPIE Vol. 1447, p. 243-250, Charge-Coupled Devices and Solid State Optical Sensors II, Morley M. Blouke; Ed.
Computer Science
Scientific paper
An update on research activities at Columbia University in the area of focal-plane image processing is presented. Two thrust areas have been pursued: image reorganization for image compression and image half-toning. The image reorganization processor is an integration of a 256 X 256 frame-transfer CCD imager with CCD-based circuitry for pixel data reorganization to enable difference encoding for hierarchical image compression. The reorganization circuitry occupies 2% of the total chip area and is performed using three parallel-serial-parallel (SP(superscript 3)) registers, a pixel resequencing block, and a sampling block for differential output. The chip has achieved a CTE of 0.99994 in this new SP(superscript 3) architecture, at an output rate of 83 X 10(superscript 3) pixels/sec. (0.9996 at 2 X 10(superscript 6) pixels/sec) and an overall output amplifier sensitivity of 3.2 (mu) V/electron. The half-toning chip design has been described previously, and consists of a 256 X 256 frame transfer imager, a pipeline register, and comparator circuit. Functional testing of these elements is reported at this time.
Eid El-Sayed I.
Fossum Eric R.
Kemeny Sabrina E.
Mendis Sunetra K.
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