VLSI implementation of a reduced symmetric fuzzy singleton set

Details VLSI implementation of a reduced symmetric fuzzy singleton set VLSI implementation of a reduced symmetric fuzzy singleton set

Aug 1993

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1993spie.2055..597c&link_type=abstract

Proc. SPIE Vol. 2055, p. 597-605, Intelligent Robots and Computer Vision XII: Algorithms and Techniques, David P. Casasent; Ed.

Mathematics

Logic

Scientific paper

A fuzzy logic controller (FLC) has been proposed and implemented in many control systems to deliver smooth and more reliable outputs than the traditional control systems. In most of the existing VLSI FLC chips, the architectures are based on general purpose microcontroller structure tailored to fuzzy logic implementation. The drawbacks in these types of FLC VLSI chips are low speed, high cost, and long design time. Moreover, an expensive development system is also needed to program a general purpose microcontroller for a specific fuzzy logic control system. In order to alleviate the drawbacks in existing VLSI fuzzy logic circuits, a reduced symmetric fuzzy singleton set (RSFSS) is proposed in this paper. The proposed RSFSS system can handle three input variables, nine rules for each input variable, and produces two output values. Each rule is based on a symmetric triangular membership function. The triangular membership functions of each state variable are defined symmetrically with respect to the centroid of the universe of discourse. Since the hardware complexity is greatly reduced, the entire FLC based on the RSFS structure can be implemented on a VLSI chip with a dimension of 2.22 mm X 2.22 mm.

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