Computer Science – Performance
Scientific paper
Nov 1999
adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1999spie.3807...50s&link_type=abstract
Proc. SPIE Vol. 3807, p. 50-61, Advanced Signal Processing Algorithms, Architectures, and Implementations IX, Franklin T. Luk; E
Computer Science
Performance
Scientific paper
This paper presents novel methods of designing analog Cellular Nonlinear (Neural) Networks (CNNs) to implement very low-noise binary addition. In these techniques the continuous characteristic of the current that charges (discharges) the load capacitor, leads to a virtually switching free addition process that significantly reduces the switching noise. This switching mechanism also leads to higher slew of output voltage during the transitions which in turn reduces the cross talk. Simulation results demonstrate a three orders of magnitude reduction in the noise generated by this structure compared to that generated by a digital adder running at the same speed. This very good noise performance of these new adder structures makes them suitable choices for low to moderate speed high precision mixed signal applications.
Jullien Graham A.
Miller Casey W.
Sadeghi-Emamchaie Saeid
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