Tree Parity Machine Rekeying Architectures

Details Tree Parity Machine Rekeying Architectures Tree Parity Machine Rekeying Architectures

2005-02-14

arxiv.org/abs/cs/0502062v1

IEEE Transactions on Computers Vol. 54 No. 4, pp. 421-427, April 2005

Computer Science

Cryptography and Security

Scientific paper

The necessity to secure the communication between hardware components in embedded systems becomes increasingly important with regard to the secrecy of data and particularly its commercial use. We suggest a low-cost (i.e. small logic-area) solution for flexible security levels and short key lifetimes. The basis is an approach for symmetric key exchange using the synchronisation of Tree Parity Machines. Fast successive key generation enables a key exchange within a few milliseconds, given realistic communication channels with a limited bandwidth. For demonstration we evaluate characteristics of a standard-cell ASIC design realisation as IP-core in 0.18-micrometer CMOS-technology.

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