The Challenges of Hardware Synthesis from C-Like Languages

Details The Challenges of Hardware Synthesis from C-Like Languages The Challenges of Hardware Synthesis from C-Like Languages

2007-10-25

arxiv.org/abs/0710.4683v1

Dans Design, Automation and Test in Europe - DATE'05, Munich : Allemagne (2005)

Computer Science

Programming Languages

Submitted on behalf of EDAA (http://www.edaa.com/)

Scientific paper

MANY TECHNIQUES for synthesizing digital hardware from C-like languages have
been proposed, but none have emerged as successful as Verilog or VHDL for
register-transfer-level design. This paper looks at two of the fundamental
challenges: concurrency and timing control.

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