Testing interconnected VLSI circuits in the Big Viterbi Decoder

Details Testing interconnected VLSI circuits in the Big Viterbi Decoder Testing interconnected VLSI circuits in the Big Viterbi Decoder

Aug 1991

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=1991tdar.nasa..175o&link_type=abstract

In its The Telecommunications and Data Acquisition Report p 175-182 (SEE N91-32250 24-32)

Mathematics

Logic

Chips (Electronics), Deep Space Network, Digital Systems, Electric Connectors, Electronic Equipment Tests, Error Correcting Codes, Very Large Scale Integration, Viterbi Decoders, Arithmetic And Logic Units, Cassini Mission, Comet Rendezvous Asteroid Flyby Mission, Computerized Simulation, Decoding, Galileo Project, Printed Circuits, Symbols

Scientific paper

The Big Viterbi Decoder (BVD) is a powerful error-correcting hardware device for the Deep Space Network (DSN), in support of the Galileo and Comet Rendezvous Asteroid Flyby (CRAF)/Cassini Missions. Recently, a prototype was completed and run successfully at 400,000 or more decoded bits per second. This prototype is a complex digital system whose core arithmetic unit consists of 256 identical very large scale integration (VLSI) gate-array chips, 16 on each of 16 identical boards which are connected through a 28-layer, printed-circuit backplane using 4416 wires. Special techniques were developed for debugging, testing, and locating faults inside individual chips, on boards, and within the entire decoder. The methods are based upon hierarchical structure in the decoder, and require that chips or boards be wired themselves as Viterbi decoders. The basic procedure consists of sending a small set of known, very noisy channel symbols through a decoder, and matching observables against values computed by a software simulation. Also, tests were devised for finding open and short-circuited wires which connect VLSI chips on the boards and through the backplane.

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