System-level tools and reconfigurable computing for next-generation HWIL systems

Details System-level tools and reconfigurable computing for next-generation HWIL systems System-level tools and reconfigurable computing for next-generation HWIL systems

Aug 2001

adsabs.harvard.edu/cgi-bin/nph-data_query?bibcode=2001spie.4366..383s&link_type=abstract

Proc. SPIE Vol. 4366, p. 383-394, Technologies for Synthetic Environments: Hardware-in-the-Loop Testing VI, Robert Lee Murrer; E

Computer Science

Performance

Scientific paper

Previous work has been presented on the creation of computing architectures called DIME, which addressed the particular computing demands of hardware in the loop systems. These demands include low latency, high data rates and interfacing. While it is essential to have a capable platform for handling and processing of the data streams, the tools must also complement this so that a system's engineer is able to construct their final system. The paper will present the work in the area of integration of system level design tools, such as MATLAB and SIMULINK, with a reconfigurable computing platform. This will demonstrate how algorithms can be implemented and simulated in a familiar rapid application development environment before they are automatically transposed for downloading directly to the computing platform. This complements the established control tools, which handle the configuration and control of the processing systems leading to a tool suite for system development and implementation. As the development tools have evolved the core-processing platform has also been enhanced. These improved platforms are based on dynamically reconfigurable computing, utilizing FPGA technologies, and parallel processing methods that more than double the performance and data bandwidth capabilities. This offers support for the processing of images in Infrared Scene Projectors with 1024 X 1024 resolutions at 400 Hz frame rates. The processing elements will be using the latest generation of FPGAs, which implies that the presented systems will be rated in terms of Tera (1012) operations per second.

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